Voltage regulators accept an input voltage (VIN) and produce a regulated output voltage (VOUT). In an ideal voltage regulator, the desired VOUT will be output by the regulator, so long as VIN is greater than or equal to VOUT. In real circuits, however, there is some voltage drop across the regulator—i.e., between VIN and VOUT—and so VIN must be greater than VOUT by at least this voltage drop. The minimum voltage required across the regulator to maintain regulation is referred to as the “dropout voltage.” Thus, in order for a voltage regulator having a dropout voltage of VDO to provide an output voltage of VOUT, VIN must be at least VOUT+VDO.
A Low-Dropout Voltage Regulator (which may be referred to herein as “an LDO voltage regulator,” “an LDO regulator,” or simply “an LDO”) is one that can regulate the output voltage even when the supply voltage is very close to the output voltage: when VDO is small, VIN can be very close to VOUT and the regulator will still operate correctly.
FIG. 1 is a circuit schematic of a conventional LDO voltage regulator 10. A typical LDO 10 uses an operational amplifier, or “op amp,” 12 to drive the control terminal of a Bipolar Junction Transistor (BJT) or Field-Effect Transistor (FET) device 14. Thus, a generic LDO 10 can be considered to be a two-stage amplifier consisting of a so-called Error Amplifier (EA) stage and an output (OUT) stage. In complementary Metal Oxide Semiconductor (MOS) process, the output stage is usually a MOS transistor, the impedance of which is controlled by the feedback loop in order to regulate the voltage at its drain. Therefore, such a regulator can be considered to be a two-stage voltage feedback amplifier.
In the conventional LDO 10 illustrated in FIG. 1, the op amp 12 may also be referred to as the error amp 12, and has a transconductance value (gmEA), while the FET 14 may also be referred to as the output amp 14, and has a transconductance value (gmOUT). The amplifier feedback signal (AFB) is provided by a voltage divider 16, comprising a resistor ladder with resistors R1 and R2 connected in series to provide a feedback voltage (VFB) to one of the input terminals of the op amp 12. The op amp 12 has an output resistance represented in FIG. 1 as a shunt resistance (RoEA). The load at the output of the LDO 10 is represented in FIG. 1 by a load resistance RLOAD and an output capacitance (COUT). A reference voltage (VREF) is provided as the input to the LDO 10 and is connected to another of the input terminals of the op amp 12
The transfer function of such a system usually includes two poles: a first pole at the output of the first amplifier stage (P1) and a second pole at the output of the second stage (P2). In the absence of compensation, these two poles are not greatly separated in frequency; thus, some compensation is needed to stabilize the system. Further, the location of the output pole (P2) in a voltage regulator is directly proportional to the load current. A typical LDO 10 is required to support a large dynamic range of load currents, which creates an additional challenge in stabilizing the system. See Equations (1) and (2).
                              R          LOAD                =                              V            OUT                                I            LOAD                                              EQ        .                                  ⁢                  (          1          )                                                  P          ⁢                                          ⁢          2                =                              1                                          R                LOAD                            ⁢                              C                out                                              ∝                                    I              load                                      C              out                                                          EQ        .                                  ⁢                  (          2          )                    where VOUT is the output voltage of the LDO 10 and ILOAD is the load current at the output terminal.
Several solutions have been disclosed in the past to stabilize a LDO 10. One form of compensation is called Miller compensation and involves placing a compensation capacitor (Cc) across the output stage (e.g., the FET 14) of the LDO 10. This compensation capacitor splits the two poles, whereby the dominant pole at P1 is moved to a lower frequency, and the pole at the output (P2) is moved to a higher frequency, thereby stabilizing the system. This is shown in FIG. 2.
FIG. 2 is a graph of the frequency response of the conventional LDO with Miller compensation. A well-known issue with Miller compensation, however, is that the compensation capacitor (Cc) creates a zero in the Right Half Plane (RHP), which may reduce stability.
FIG. 3 is a circuit schematic of a conventional Miller-compensated LDO 18 that uses a nulling resistor (RZ) in series with the compensation capacitor (Cc) to solve the RHP zero problem. To support a large dynamic range of load currents, the compensation capacitor (CC) must be chosen to be large enough for the system to be stable for the lowest load current. This has a negative effect on the bandwidth and transient response of the conventional Miller-compensated LDO 18.
FIG. 4 is a circuit schematic of a conventional Miller-compensated LDO 20 that uses a current buffer 22 in series with the compensation capacitor (Cc) to solve the RHP zero problem in a more robust way. This current buffer 22 eliminates the forward path and hence the RHP zero as shown in FIG. 4. A common implementation of such a circuit is also called “Ahuja compensation” or “cascode compensation”. Another advantage of this compensation technique is that it introduces a Left Half Plane (LHP) zero, which further helps in stabilizing the system. See also Equation (3).
                              LHP          zero                =                  -                                    gm              CG                                      C              c                                                          EQ        .                                  ⁢                  (          3          )                    where gmCG is the transconductance of the P-Type MOS (PMOS) transistor that connects the output of the error amplifier 12 to the compensation capacitor having a capacitance value (Cc). FIG. 4 also shows the equivalent circuit of the current buffer 22 and compensation capacitor (Cc): the current buffer 22 operates as a resistor to ground having an impedance of 1/gmCG. The frequency of the zero introduced by the current buffer 22 is a function of the values of the transconductance (gmCG) and the capacitance (Cc).
FIG. 5 is a circuit schematic of a conventional Miller-compensated LDO 24 that uses another method for solving the RHP zero issue in Miller compensation, which is to use the so-called split-length MOS compensation. In this approach, an error amplifier 26 includes a low-impedance node created by splitting a MOS transistor—for instance, one of the input MOS pair of a conventional op amp—and placing each part in series. In FIG. 5, one of the pair of input MOS transistors has been split into two MOS transistors connected in series, Mn1A and Mn1B, while the other of the pair of input MOS transistors has been split into another two MOS transistors connected in series, Mn2A and Mn2B. For each set of series connected MOS transistors, the gates of the two series-connected MOS transistors are connected together. As a result, the MOS transistor placed at the source side (Mn2B) is in triode mode and has a transconductance of gm; its impedance can be approximated to 1/gm. The MOS transistor (Mn2A) operates as a buffer amplifier 28 and has a transconductance of gmBUF.
The compensation capacitor (Cc) is placed at the low-impedance node between the two MOS transistors in series, e.g., between Mn2A and Mn2B in FIG. 5. This splitting of MOS transistors results in effectively nulling the RHP zero and introducing a LHP zero, which is at a frequency proportional to gmBUF/Cc.
The cascode compensation (Ahuja compensation) and split-length MOS compensation techniques are sometimes grouped together and referred to as indirect Miller compensation. They are referred to as such in the remainder of the present disclosure.
FIG. 6 represents a general indirect Miller-compensated LDO 30 that contains the error amplifier 26, the output amplifier 14, and the buffer amplifier 28. The amplitude of the feedback signal will be some fraction of the output voltage (VOUT); this is represented in FIG. 6 by voltage divider 16, which may represent a resistor ladder or other circuit that provides a feedback signal with amplitude (VOUT/M). Each amplifier drawn can consist of one or more stages. As discussed previously, this system has two main poles: P1 at the output of the first amplifier stage and P2 at the output of the second amplifier stage.
However, the output pole (P2) of this system varies with load current, and because of this, the dominant pole (P1) needs to be at a relatively low frequency in order to avoid instability in the LDO 30. In addition, the transconductance of the buffer amplifier 28, gmBUF, introduces a LHP zero that is located at gmBF/Cc. See also Equations (4) to (6).
                              P          ⁢                                          ⁢          1                ∝                              Rout            EA                                              A              OUT                        ⁢            Cc                                              EQ        .                                  ⁢                  (          4          )                                                  P          ⁢                                          ⁢          2                ∝                              I            LOAD                    Cc                                    EQ        .                                  ⁢                  (          5          )                                                  LHP          zero                =                  -                                    gm              BUF                                      C              c                                                          EQ        .                                  ⁢                  (          6          )                    where RoutEA is the output resistance of the error amplifier 26, AOUT is the gain of the output amplifier 14, and (Cc) is the value of the compensation capacitor.
In summary, Miller compensation and its variants have a fundamental drawback in terms of limitation placed on the bandwidth of the system: because the output pole varies with load, the dominant pole has to be at a lower frequency than desired. This affects both the wideband power supply rejection ratio and transient response of the LDO, where stability needs to be ensured for a wide dynamic range of load currents.